Interrupts

What Is an Interrupt?

An interrupt is a signal sent to the CPU that temporarily halts the current program execution so that another, more urgent task can be attended to.

Think of it like a fire alarm — no matter what you’re doing, you must stop and respond.

Once the interrupt is handled, the CPU returns to its previous task as if nothing happened.

1. Why Interrupts Exist

Interrupts allow computers to be:

Responsive to real-world events (e.g., mouse clicks, network packets)
Efficient by eliminating constant polling
Multitasking-capable, enabling asynchronous operations

Without interrupts, CPUs would need to constantly check for events — a wasteful process called polling.

2. Types of Interrupts

Type	Trigger Source	Examples
Hardware Interrupt	External devices	Keyboard input, mouse, disk I/O
Software Interrupt	CPU instructions	System calls, `int` in x86
Timer Interrupt	Periodic timer signals	Multitasking, scheduling
Spurious Interrupt	Electrical noise or bugs	Unexpected or unrecognized signals
Non-Maskable Interrupt (NMI)	Critical hardware failure	Power loss, memory parity errors

3. Interrupt Handling Overview

When an interrupt occurs:

CPU pauses current execution
It saves context (registers, program counter)
Jumps to a specific interrupt handler
Executes the handler routine
Restores context and resumes execution

This is known as the Interrupt Handling Cycle.

4. Interrupt Vector Table

To manage multiple interrupt sources, systems use an Interrupt Vector Table (IVT):

A lookup table mapping interrupt numbers to handler addresses
Stored in memory at a well-known location (e.g., 0x0000:0000 in x86 real mode)

Interrupt #	Description	Address
0	Divide by zero	0x0000:0000
13	General protection	0x0000:0340
32	Timer tick (IRQ0)	0x0000:0800

5. Maskable vs Non-Maskable Interrupts

Maskable Interrupts (IRQs): Can be enabled/disabled by the CPU
Non-Maskable Interrupts (NMI): Always processed; cannot be disabled

Masking allows CPUs to defer interrupt handling during critical sections.

6. Hardware Interrupts in Detail

Common examples:

Keyboard: Sends signal when key is pressed
Disk Controller: Notifies when I/O is done
Network Card: Indicates packet received

These are handled via Interrupt Requests (IRQs):

IRQ0 → System timer
IRQ1 → Keyboard
IRQ14 → Primary ATA channel

Modern systems use Advanced Programmable Interrupt Controllers (APIC) to manage interrupts more flexibly.

7. Software Interrupts

Generated by instructions like int in x86 assembly:

int 0x80  ; Linux system call interrupt

Used for:

System calls (trap into kernel mode)
Debugging (breakpoints)
Fault handling (divide by zero, page fault)

Trap vs Interrupt:

Trap = Synchronous (caused by executing instruction)
Interrupt = Asynchronous (external event)

8. Interrupt Service Routine (ISR)

An ISR is a small function that handles a specific interrupt.

ISR duties:

Acknowledge the interrupt
Perform necessary task (e.g., read data)
Possibly signal the OS (via a flag or queue)
Return control using special instructions (e.g., IRET in x86)

ISRs must be:

Fast
Reentrant (able to be safely interrupted)
Minimal (do the bare minimum, defer complex work)

9. Interrupt Prioritization and Nesting

Systems often allow interrupt nesting:

A higher-priority interrupt can interrupt an ISR
Priority levels are managed via the interrupt controller

Priority	Source
High	Power failure, NMI
Medium	Keyboard, disk I/O
Low	Timer, software requests

To prevent infinite nesting, the system can disable lower-priority interrupts during ISR execution.

10. Real-World Use Cases

Use Case	Interrupt Role
Real-time clocks	Send regular interrupts for scheduling
Keyboard input	Generate interrupt on keypress
Multitasking	Use timer interrupts to switch tasks
I/O operations	Notify when data is ready or transferred
Embedded systems	Handle button presses, sensor signals, etc.

11. Interrupts in OS Design

Modern operating systems rely heavily on interrupts for:

Context switching (via timer interrupt)
Device drivers (interrupt-driven I/O)
Signals and syscalls

The kernel sets up ISRs during boot and maps them in its interrupt descriptor table (IDT).

12. Interrupt Storms and Debouncing

Interrupt storms: Too many interrupts overwhelm the CPU (common in network-heavy environments)

Solutions:

Interrupt throttling
Polling fallback
Message-signaled interrupts (MSI)

Debouncing: Preventing multiple interrupts from a single button press (common in hardware/embedded)

13. Alternatives to Interrupts

Method	Description
Polling	Constantly check for events in a loop (inefficient)
DMA (Direct Memory Access)	Device writes to memory directly, reducing interrupt frequency
Hybrid Models	Polling + Interrupt combo for balanced performance

Summary

Aspect	Description
Definition	CPU halts current task to handle an event
Types	Hardware, software, timer, spurious
Key Components	IVT/IDT, ISR, IRQs, PIC/APIC
Usage	Input handling, scheduling, I/O, system calls
Handling Cycle	Save context → Jump to ISR → Return
OS Role	Manages ISRs, maps devices, enables multitasking
Risks	Storms, race conditions, missed interrupts